IEEE Transactions on Intelligent Transportation Systems
Simulation results of a publication entitled Time-Optimal Maneuver Planning in Automatic Parallel Parking Using a Simultaneous Dynamic Optimization ...
柏李
IEEE CIS "How to publish your research": Garrison Greenwood
Location: IEEE Congress on Evolutionary Computation 2013 (http://www.cec2013.org/) Panel Discussion "How to publish your research", June 21, 4-6pm Chair: ...
CIS Cyprus
2018 IEEE Transactions on Image Processing topics with abstract
IEEE IMAGE PROCESSING projects 2018 topic with abstract for Final Year Students.
Tsys Globalsolutions
Publishing your research, by Marios Polycarpou
5th Cyprus Workshop on Signal Processing and Informatics (CWSPI) University of Cyprus, Nicosia, Cyprus July 10, 2012 *** Due to a technical problem this ...
Demetrios Eliades
PETCAM — A Power Efficient TCAM Architecture For Forwarding Tables: Video extra
In this video, coauthor Tania Banerjee-Mishra gives an overview of Ternary Content Addressable Memory and explains how the PETCAM approach improves ...
ieeeComputerSociety
Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores...Spanish
All the cores of a many-core chip cannot be active at the same time, due to reasons like low CPU utilization in server systems and limited power budget in dark ...
ieeeComputerSociety
Gestión de Potencia Escalable para sistemas en chip con aplicaciones maleables (Spanish) 1116
Abstract—We present a scalable Dynamic Power Management (DPM) schem e where malleable applications may change their degree of parallelism at run time ...
ieeeComputerSociety
Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded Microprocessors (0318) Chinese
The risk of code reverse-engineering is particularly acute for embedded processors which often have limited available resources to protect program information.
ieeeComputerSociety
Deadlock Verification of Cache Coherence Protocols and Communication Fabrics 0217 Spanish
Cache coherence plays a major role in manycore systems. The verification of deadlocks is a challenge in particular, because deadlock freedom is an emerging ...
ieeeComputerSociety
Contention-Aware Fair Scheduling for Asymmetric Single-ISA Multicore Systems (1218) Spanish
Asymmetric single-ISA multicore processors (AMPs), which integrate high-performance big cores and low-power small cores, were shown to deliver higher ...
ieeeComputerSociety
Revisiting Vulnerability Analysis in Modern Microprocessors
The notion of Architectural Vulnerability Factor (AVF) has been extensively used to evaluate various aspects of design robustness. While AVF has been a very ...
ieeeComputerSociety
A Novel Coding Scheme for Secure
E-SYSTEMS-TECHNO PVT LTD Website: www.esystems.co.in Email Id : info@esystems.co.in Phone: + 91 868 652 2186 + 91 868 652 2184 A-2, Ground Floor, ...
Ieee Projects
On-Chip Communication Network for Efficient Training of Deep Convolutional Networks...(Chinese)
Convolutional Neural Networks (CNNs) have shown a great deal of success in diverse application domains including computer vision, speech recognition, and ...
ieeeComputerSociety
Polysynchronous Clocking: Exploiting the 2 Skew Tolerance of Stochastic Circuits Spanish 1017
In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method 6 naturally and effectively tolerates very high ...
ieeeComputerSociety
Node Scaling Analysis for Power-Aware Real-Time Tasks Scheduling Chinese (0816)
Multi-core processors achieve a trade-off between the performance and the power consumption by using Dynamic Voltage Scaling (DVS) techniques. In this ...
ieeeComputerSociety
Efficient Detection for Malicious and Random Errors in Additive Encrypted Computation Spanish (0118)
Although data confidentiality is the primary security objective in additive encrypted computation applications, such as the aggregation of encrypted votes in ...
ieeeComputerSociety
Everything You Need to Know About 5G
Millimeter waves, massive MIMO, full duplex, beamforming, and small cells are just a few of the technologies that could enable ultrafast 5G networks.
IEEE Spectrum
Generation of Models for Wireless Sensor Network Assessment
Authors Domenico Cotroneo, Catello Di Martino, and Marcello Cinque discuss the use of wireless sensor networks for building the next generation of critical ...
ieeeComputerSociety
Deadlock Verification of Cache Coherence Protocols and Communication Fabrics
Cache coherence plays a major role in manycore systems. The verification of deadlocks is a challenge in particular, because deadlock freedom is an emerging ...
ieeeComputerSociety
Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores...(Chinese)
All the cores of a many-core chip cannot be active at the same time, due to reasons like low CPU utilization in server systems and limited power budget in dark ...
ieeeComputerSociety
Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manicure...0117 Spanish
Chip manufacturers provide the Thermal Design Power (TDP) for a specific chip. The cooling solution is designed to dissipate this power level. But because TDP ...
ieeeComputerSociety
Bulletproofs: Short Proofs for Confidential Transactions and More
Bulletproofs: Short Proofs for Confidential Transactions and More Benedikt Bünz (Stanford University) Presented at the 2018 IEEE Symposium on Security ...
IEEE Symposium on Security and Privacy
Arb: Efficient Arbitrary-Precision 2 Midpoint-Radius Interval Arithmetic Spanish (0817)
Arb is a C library for arbitrary-precision interval arithmetic using the midpoint-radius representation, also known as ball arithmetic. It supports real and complex ...
ieeeComputerSociety
Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache (0517)-Chinese
For the sake of higher cell density while achieving near-zero standby power, recent research progress in Magnetic Tunneling Junction (MTJ) devices has ...
ieeeComputerSociety
Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip-Chinese
Reliability is one of the most challenging problems in the context of three-dimensional network-on-chip (3D NoC) systems. Reliability analysis is prominent for ...
ieeeComputerSociety
Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded Microprocessors Spanish (0318)
The risk of code reverse-engineering is particularly acute for embedded processors which often have limited available resources to protect program information.
ieeeComputerSociety
Configurable XOR Hash Functions for Banked Scratchpad Memories in GPUs (0716 Chinese)
Scratchpad memories in GPU architectures are employed as software-controlled caches to increase the effective GPU memory bandwidth. Through the use of ...
ieeeComputerSociety
Efficient Detection for Malicious and Random Errors in Additive Encrypted Computation Chinese (0118)
Although data confidentiality is the primary security objective in additive encrypted computation applications, such as the aggregation of encrypted votes in ...
ieeeComputerSociety
Lec 23: How to Explore Computer Architecture?
Advanced Computer Architecture Course URL: https://swayam.gov.in/nd1_noc19_cs62/... Prof. John Jose Dept of Computer Science & Engineering IIT ...
NPTEL IIT Guwahati
Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors - March Chinese
With increasing transistor density on a single chip, processor design in the nanoscale era is hitting power and frequency walls. Due to these challenges, ...
ieeeComputerSociety
Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale... Chinese 0616
As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. The Helix-h non-blocking ...
ieeeComputerSociety
Advance Virtual Channel Reservation Chinese 0920
We present a smart communication service called Advance Virtual Channel Reservation (AVCR) to provide a highway to target packets, which can greatly ...
ieeeComputerSociety
Deadlock Verification of Cache Coherence Protocols and Communication Fabrics 0217 Chinese
Cache coherence plays a major role in manycore systems. The verification of deadlocks is a challenge in particular, because deadlock freedom is an emerging ...
ieeeComputerSociety
In Their Own Words: Naga Durga Prasad Avirneni, and Arun Somani
The threat of soft error induced system failure in computing systems has become more prominent, as we adopt ultra-deep submicron process technologies.
ieeeComputerSociety
IEEE Transactions on Signal Processing Top #5 Facts
Rishika Janaki
SPACE: Semi-Partitioned CachE for Energy Efficient, Hard Real-Time Systems Spanish 0417
Abstract—Multi-core processors are increasingly popular because they yield higher performance, but they also present new challenges for hard real-time ...
ieeeComputerSociety
IEEE TRANSACTION ON SECURITY TOPICS 2017
IEEE Information security projects 2017 for Final Year Students Information security, sometimes shortened to InfoSec, is the practice of defending information ...
Tsys Globalsolutions
Static Instruction Scheduling for High Performance on Limited Hardware (0518)
Complex out-of-order (OoO) processors have been designed to overcome the restrictions of outstanding long-latency misses at the cost of increased energy ...
ieeeComputerSociety
Managing data chaos with intelligent computational memory | Evangelos Eleftheriou | TEDxChalkida
Data, memory and neuromorphic computing. Dr. Enangelos Eleftheriou explains how mimicking nature we can create more efficient computing systems and ...
TEDx Talks
How to use the Encyclopaedia of Forms & Precedents
This is for students of Temasek Polytechnic who have access to the Library website http://spark.tp.edu.sg.
Benjamin Ang
Enhancing Energy Efficiency of Multimedia Applications in Heterogeneous Mobile...Spanish (1117)
Abstract—Recent smart devices have adopted heterogeneous multi-core processors which have high-performance big cores and 6 low-power small cores.
ieeeComputerSociety
Stanford Seminar - New Golden Age for Computer Architecture
EE380: Computer Systems Colloquium Seminar New Golden Age for Computer Architecture: Domain-Specific Hardware/Software Co-Design, Enhanced ...
stanfordonline
